1. Field of the Invention
The present invention relates to a method of writing data to a dynamic random access memory.
2. Description of the Related Art
A synchronous dynamic random access memory must have a large capacity, and must be capable of high-speed operation. However, if the capacity of the memory becomes large, a load on wiring is increased. Therefore, access speed is reduced. To solve this problem, a memory device which has a plurality of memory cell blocks is developed. However, in this memory device, a size of the memory device is increased. Another memory device which has two sets of data buses and read amplifiers has been developed. In such type of memory device, each set is operated alternatively.
Another DRAM for operating high-speed is described in reference 1: Japanese patent Laid-Open No. 8-87879 and reference 2: Japanese Patent Laid-Open No. 12-149562. The reference 1 discloses an SDRAM for visual data which performs a block write operation. In the SDRAM of reference 1, data is written to sense amplifiers while bit lines are disconnected from the sense amplifiers, and then, the data is transferred from the sense amplifiers to the bit lines.
In the DRAM disclosed in reference 2, data is amplified in a sense amplifier after a small voltage which is generated in a bit line pair is transferred to the sense amplifier and the bit line pair is disconnected from the sense amplifier. Therefore, a reading speed is increased.
However, the reference 1 does not disclose a high-speed technique for a general purpose DRAM, because the reference 1 discloses a high-speed technique for a visual data DRAM. Also the reference 2 does not disclose a high-speed writing operation. Therefore a high-speed writing operation for a general purpose DRAM is desired.